1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
|
// --------------------------------------------------------------------
// Copyright (c) 2008 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: support@terasic.com
//
// --------------------------------------------------------------------
//
// Major Functions: control_interface
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 08/04/22 :| Initial Revision
// --------------------------------------------------------------------
module control_interface(
CLK,
RESET_N,
CMD,
ADDR,
REF_ACK,
INIT_ACK,
CM_ACK,
NOP,
READA,
WRITEA,
REFRESH,
PRECHARGE,
LOAD_MODE,
SADDR,
REF_REQ,
INIT_REQ,
CMD_ACK
);
`include "Sdram_Params.h"
input CLK; // System Clock
input RESET_N; // System Reset
input [2:0] CMD; // Command input
input [`ASIZE-1:0] ADDR; // Address
input REF_ACK; // Refresh request acknowledge
input INIT_ACK; // Initial request acknowledge
input CM_ACK; // Command acknowledge
output NOP; // Decoded NOP command
output READA; // Decoded READA command
output WRITEA; // Decoded WRITEA command
output REFRESH; // Decoded REFRESH command
output PRECHARGE; // Decoded PRECHARGE command
output LOAD_MODE; // Decoded LOAD_MODE command
output [`ASIZE-1:0] SADDR; // Registered version of ADDR
output REF_REQ; // Hidden refresh request
output INIT_REQ; // Hidden initial request
output CMD_ACK; // Command acknowledge
reg NOP;
reg READA;
reg WRITEA;
reg REFRESH;
reg PRECHARGE;
reg LOAD_MODE;
reg [`ASIZE-1:0] SADDR;
reg REF_REQ;
reg INIT_REQ;
reg CMD_ACK;
// Internal signals
reg [15:0] timer;
reg [15:0] init_timer;
// Command decode and ADDR register
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
NOP <= 0;
READA <= 0;
WRITEA <= 0;
SADDR <= 0;
end
else
begin
SADDR <= ADDR; // register the address to keep proper
// alignment with the command
if (CMD == 3'b000) // NOP command
NOP <= 1;
else
NOP <= 0;
if (CMD == 3'b001) // READA command
READA <= 1;
else
READA <= 0;
if (CMD == 3'b010) // WRITEA command
WRITEA <= 1;
else
WRITEA <= 0;
end
end
// Generate CMD_ACK
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
CMD_ACK <= 0;
else
if ((CM_ACK == 1) & (CMD_ACK == 0))
CMD_ACK <= 1;
else
CMD_ACK <= 0;
end
// refresh timer
always @(posedge CLK or negedge RESET_N) begin
if (RESET_N == 0)
begin
timer <= 0;
REF_REQ <= 0;
end
else
begin
if (REF_ACK == 1)
begin
timer <= REF_PER;
REF_REQ <=0;
end
else if (INIT_REQ == 1)
begin
timer <= REF_PER+200;
REF_REQ <=0;
end
else
timer <= timer - 1'b1;
if (timer==0)
REF_REQ <= 1;
end
end
// initial timer
always @(posedge CLK or negedge RESET_N) begin
if (RESET_N == 0)
begin
init_timer <= 0;
REFRESH <= 0;
PRECHARGE <= 0;
LOAD_MODE <= 0;
INIT_REQ <= 0;
end
else
begin
if (init_timer < (INIT_PER+201))
init_timer <= init_timer+1;
if (init_timer < INIT_PER)
begin
REFRESH <=0;
PRECHARGE <=0;
LOAD_MODE <=0;
INIT_REQ <=1;
end
else if(init_timer == (INIT_PER+20))
begin
REFRESH <=0;
PRECHARGE <=1;
LOAD_MODE <=0;
INIT_REQ <=0;
end
else if( (init_timer == (INIT_PER+40)) ||
(init_timer == (INIT_PER+60)) ||
(init_timer == (INIT_PER+80)) ||
(init_timer == (INIT_PER+100)) ||
(init_timer == (INIT_PER+120)) ||
(init_timer == (INIT_PER+140)) ||
(init_timer == (INIT_PER+160)) ||
(init_timer == (INIT_PER+180)) )
begin
REFRESH <=1;
PRECHARGE <=0;
LOAD_MODE <=0;
INIT_REQ <=0;
end
else if(init_timer == (INIT_PER+200))
begin
REFRESH <=0;
PRECHARGE <=0;
LOAD_MODE <=1;
INIT_REQ <=0;
end
else
begin
REFRESH <=0;
PRECHARGE <=0;
LOAD_MODE <=0;
INIT_REQ <=0;
end
end
end
endmodule
|
